A memory device having a three-dimensional structure has been proposed. In the memory device, a memory hole is formed in a stacked body including a plurality of electrode layers stacked via insulating layers. The electrode layers function as control gates in memory cells. A silicon body functioning as a channel is provided on the sidewall of the memory hole via a charge storage film.
In order to reduce a space factor of a control circuit of a three-dimensional memory array in a chip, there has also been proposed a technique for providing the control circuit right under the array. For example, a configuration is proposed in which bit lines are connected to transistors formed on a substrate, via contact plugs formed at an array end portion and a bit line extension layer provided on the lower side of a memory array.
Therefore, a fine interconnection layer equivalent to the bit lines is also necessary under the array. A region around the array is necessary in order to form a deep contact. Further, there is a concern about a problem in that, for example, the bit lines are substantially long, a bit line capacity increase, and operation speed is affected.